1. Field of the Invention
The present invention generally relates to a chip classifying method for judging the quality of chips on a wafer in a process of manufacturing semiconductor devices (chips), a chip classifying program, a chip quality judgment program, a marking mechanism, and a method of manufacturing semiconductor devices.
2. Description of the Related Art
A semiconductor device becomes a product through various manufacturing processes. Unfortunately, various problems in those processes may cause reduction of the device yield and the quality of the devices. To detect such defective products in the manufacturing processes, the electric characteristics of each product (chip) on a wafer have been tested (wafer test) to determine whether the chip is good or defective after the patterns of the chips are formed through various processes. Then, marks are placed onto the detected defective chips in an ink marking process. Basically, the chips to be marked are determined based on the result of the wafer test. However, it is known that the defective chips may be concentrated in a part of the wafer, forming a defective chip concentrated distribution area. From experiences, when such a defective chip concentrated distribution area is formed, even though the chips have been judged as good in a wafer test, when the chips are located contiguous to or in the vicinity of the defective chip concentrated distribution area, the quality of the chips may not be sufficiently guaranteed.
Under the circumstance, a wafer having a detected defective chip concentrated distribution area has been conventionally discarded. By doing this, the quality of the products using the chips taken from wafers has been guaranteed. However, the loss due to discarding wafers cannot be avoided. Unfortunately, the loss is increasing in trend as the size of the wafer is becoming larger and larger.
On the other hand, depending on a distribution status of the defective chips on a wafer, there may be cases where good chips having sufficient quality to be guaranteed are included in the same wafer. There are various types of the problems on a wafer. For example, some troubles may be related to a status of a boundary of a single shot by a stepper in a photoengraving step due to, for example, insufficient exposure in the shot by the stepper. However actually, most of the causes are not related to such a status of the boundary but include an abnormal discharge in an etching step. Further, in most cases where the cause of a trouble on a wafer is not related to the status of the boundary a single shot by a stepper, there is a tendency that influence of a trouble is reduced with increasing distance from a center of the defective chip concentrated distribution area.
To avoid discarding wafers, the result of the wafer test is visually checked so that good chips contiguous to and in the vicinity of the defective chip concentrated distribution area are treated as defective chips, and marks are placed onto the defective chips so as to be distinguished from good chips. Hereinafter, an operation of treating such good chips contiguous to and in the vicinity of the defective chip concentrated distribution area as defective and placing marks onto the defective chips so as to be recognized as defective chips is referred to as “an additional inking”.
Conventionally, there are two types of additional inking methods. One type of method is to perform inking directly onto a wafer, and the other type of method is to process the wafer test result before placing marks. Generally, as the former method, the additional inking is performed by using an inker function of a testing prober. On the other hand, as the latter method, the additional inking is performed by using a prober dedicated to the additional inking without using the inker function of the testing prober (hereinafter referred to as “a marking prober”).
When the former method of performing the additional inking directly onto a wafer is employed, the additional inking is performed onto the chips that seem to have a quality problem after a visual check based the result of the wafer test so that the additional inking is performed on the wafer.
On the other hand, when the latter method of processing the result of the wafer test is employed, the additional inking is performed onto the chips that seem to have a quality problem while the wafer test data are displayed on a display using dedicated software (program).
Further, recently, an inkless method may be used where no mark for distinguishing the defective chips is placed onto a wafer and the next process is performed based on electronic information indicating the result of the wafer test. Hereinafter, in such an inkless method, a process of changing the electronic information indicating good chips whose quality cannot be sufficiently guaranteed into the information indicating defective chips is also referred to as the “additional inking”.
By doing the above operation, the quality of the chips may be guaranteed. However, the selection of the chips that may have a quality problem is performed based on sensory analysis from the experience of operators. Therefore, disadvantageously, the result of the selection may vary depending on the operators. Furthermore, it takes many labor-hours to select chips that may have a problem, and the labor-hours are increasing in trend as the size of wafers is increased.
To solve the problems, the present inventor has developed an algorithm for analyzing the distribution of defective chips on a wafer and predicting the chips that may have a quality problem (refer to Japanese Patent No. 3888938).
However, there are many distribution patterns of defective chips. Therefore, in some cases, it may not possible to predict all the chips that should be classified as the targets of the additional inking. One of such cases is next described with reference to FIGS. 38 and 39.
FIG. 38 shows an example of the final result of the wafer test in a wafer test process. FIG. 39 shows an example where additional-inking target chips within a prescribed range of the defective chip concentrated distribution area on the wafer are classified based on a conventional method of classifying the additional-inking target chips.
As shown in FIG. 38, plural chips are arranged in a matrix in the X axis and the Y axis directions of the wafer.
Further, no marks are placed onto the chips (such as good chips 203, 205, and 207) that have been judged as good, and “X” marks are placed onto the chips (such as defective chip 209) that have been judged as defective.
According to a method of judging the defective chip concentrated distribution area disclosed in the Japanese Patent No. 3888938, the plural chips including the defective chip 209 shown in FIG. 38 are judged as the single defective chip concentrated distribution area. Further, as shown in FIG. 39, the good chips such as a good chip 205 next to the defective chip included in the defective chip concentrated distribution area, in other words, the good chips within one-chip range of the defective chips are judged as the additional-inking target chips (see bold frame line in FIG. 39).
In FIG. 39, the good chip 207 surrounded by the defective chip concentrated distribution area but separated by two chips from the defective chips in the defective chip concentrated distribution area is not judged as the additional-inking target chip. However, from experiences, there is a high likelihood that a chip such as good chip 207 within a closed area surrounded by defective chips has a quality problem.
To make it possible to automatically judge the good chip 207 surrounded by defective chips as the additional-inking target chip, the chips separated by two chips from the defective chips in the defective chip concentrated distribution area are judged as defective chips.
However, when this judgment is made, the good chip 203 separated by two chips from the defective chips in the defective chip concentrated distribution area is also judged as the defective chip. As a result, the good chip 203 is judged as the additional-inking target chip. This is not a good result because the good chip 203 has lower likelihood of having a quality problem because the good chip 203 is not surrounded by the defective chips.
Such problems can be avoided when the good chip may be classified according to the quality degradation concern levels.
Such problems may also be avoided when the chip in the vicinity of the defective chip concentrated distribution area can be classified according to the quality degradation concern levels.